TSMC says the N3 chips will be offered in three fin configuration options.
TSMC's N3 chips will utilise FinFlex architectural technology
Photo Credit: TSMC
Taiwan Semiconductor Manufacturing Company (TSMC) has announced that its chips manufactured on 3nm fabrication process will be coming in 2023, and the ones made with 2nm process will debut in 2025. At the TSMC 2022 Technology Symposium, the chipmaker also announced a new technology, FinFlex, that it will use to make the N3 and N3E chipsets. The technology is said to provide manufacturers the versatility to offer high performance, lower power consumption, and maximum transistor density based on three-fin configuration options.
As per the announcement made at the symposium, the chipsets made by N3 technology, or 3nm manufacturing process, will go into volume production later in 2022. The 3nm node will debut in five tiers: N3, N3E (Enhanced), N3P (Performance Enhanced), N3S (Density Enhanced), and N3X (Ultra High Performance). The N3 chips will use FinFlex architectural technology and will be offered in three configuration options: 3-2 fin, 2-2 fin, and 2-1 fin.
N3 performance and power efficiency configuration comparison with N5
Photo Credit: TSMC
“Before TSMC N3 and FinFlex, chip designers often had to make difficult choices between speed, power consumption, and chip density,” the company said. The new methodology is said to “enable full optimisation of the N3 design library” resulting in high performance, efficient computing, and maximising transistor density.
The 3-2 fin configuration is for those who want highest performance, the 2-2 fin configuration offers a balance between performance, power efficiency, and density. Lastly, the 2-1 fin configuration is for those who want great power efficiency and highest density.
Coming to N2 technology; the chipsets manufactured by the 2nm fabrication process are scheduled to go into production in 2025. These SoCs will be even more powerful and efficient than the 3nm ones. As per the TSMC, 2nm chips will offer 10-15 percent speed improvement at the same power, or 25-30 percent power reduction at the same speed. The technology will feature nanosheet transistor architecture “to deliver a full-node improvement in performance and power efficiency.” N2 is scheduled to begin production in 2025.
Catch the latest from the Consumer Electronics Show on Gadgets 360, at our CES 2026 hub.