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UFS 5.0 With Faster Data Access, Higher Sequential Performance Announced as Development Nears Completion

UFS 5.0 is ideal for applications where power efficiency is a critical measure, as per the company.

UFS 5.0 With Faster Data Access, Higher Sequential Performance Announced as Development Nears Completion

Photo Credit: Unsplash/Akshat Sharma

UFS 5.0 will succeed the current UFS 4.x flash storage standard

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Highlights
  • UFS 5.0 targets high-performance devices with low power consumption
  • The new standard is backward compatible with UFS 4.x hardware
  • It introduces link equalisation, in-line hashing for better reliability
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The Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association on Monday announced that its upcoming Universal Flash Storage (UFS) standard is nearing completion. Expected to debut in the future as UFS 5.0, it is claimed to be designed for mobile applications and computer systems that require high performance, while maintaining low power consumption. Compared to its predecessor, the upcoming UFS standard will bring faster data access and improved sequential performance, while also being compatible with UFS 4.x hardware.

UFS 5.0 Announced

The company says that UFS 5.0 has been designed to meet the demands of artificial intelligence (AI) applications. This is aided by an improved sequential performance, which is expected to reach speeds of up to 10.8Gbps. The upcoming flash storage standard is claimed to have improved reliability, too.

The UFS 5.0 standard is said to be in development in compliance with JEDEC's JC-64.1 Subcommittee for Electrical Specifications and Command Protocols. The company says that its ideal use cases include applications where power efficiency is critical. It includes smartphones, wearables, automotive applications, edge computing, and gaming consoles.

To maintain the signal integrity with such high data speeds, JEDEC is leveraging link equalisation to actively compensate for signal degradation. As per the company, UFS 5.0 will also use a distinct power supply rail to address electrical noise in the system. It is also said to ensure noise isolation between the physical layer (PHY) and the memory subsystem.

Meanwhile, UFS 5.0 will use in-line hashing, a mechanism that checks for the integrity of the data as it is being transferred or stored. Traditionally, this is performed by hashing calculation done in real time.

To ensure high performance and power-efficient data transport, UFS leverages specifications from the MIPI Alliance to form its Interconnect Layer, which manages the physical and link-level connection between the UFS host and the UFS device. UFS 5.0, specifically, uses the upcoming MIPI M-PHY version 6.0 specification and the UniPro version 3.0 specification. The former is claimed to support almost double the data rates of the previous HS-G5.

Consequently, it will enable the UFS interface bandwidth of 46.6Gbps per lane and up to 10.8Gbps effective read and write operations over two M-PHY lanes.

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Further reading: UFS, UFS 5.0, JEDEC
Shaurya Tomer
Shaurya Tomer is a Sub Editor at Gadgets 360 with 2 years of experience across a diverse spectrum of topics. With a particular focus on smartphones, gadgets and the ever-evolving landscape of artificial intelligence (AI), he often likes to explore the industry's intricacies and innovations – whether dissecting the latest smartphone release or exploring the ethical implications of AI advancements. In his free time, he often embarks on impromptu road trips to unwind, recharge, and ...More
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