Peking University’s 3-Layer Cooling System Handles Record Chip Heat Loads

Peking University’s 3-layer microfluidic cooler handles 3,000 W/cm² heat efficiently, enabling smaller, energy-smart chips

Updated: 10 November 2025 22:17 IST

Highlights

3-layer silicon design cools 3,000 W/cm² efficiently
Combines manifold, microjet, and microchannel cooling
Enables smaller, energy-efficient future chip designs

Peking University’s 3-layer silicon cooler efficiently handles 3,000 W/cm² heat with low power use

Photo Credit: Wikimedia Commons

In‍‌‍‍‌‍‌‍‍‌ a bid to cram more power into smaller chips while maintaining their size, the chips get heated very intensely to a point where the circuits can be damaged. One way to fix this is microfluidic cooling – which involves flooding very small channels with fluid in order to cool – and it is a very attractive method. Standard microfluidic systems have a capacity limitation of about 2,000 W/cm² heat flux, however, the team of Peking University headed by Zhihu Wu developed a three-layer cooling silicon device that achieves 3,000 W/cm² with a pumping power of only 0.9 ‍‌‍‍‌‍‌‍‍‌W/cm².

Three-Layer Cooling Design

According to the research, Wu's team etched all cooling features into the backside of a silicon chip using standard MEMS fabrication. They describe it as "a three-tier structure" with a tapered manifold layer on top, a microjet layer in the middle and a microchannel layer at the bottom. The manifold spreads coolant evenly, the microjets are tiny nozzles that spray fluid directly at the chip's hot surface, and the microchannels carry the warmed liquid away. This multi-layered design targets the thermal boundary – the thin fluid layer where chip heat concentrates – boosting heat transfer into the coolant.

Performance and Potential

The machine achieved a coefficient of performance (COP) of approximately 13,000 - 1 W of pump energy removed approximately 13,000 W/cm 2--and dissipated 1000 W /cm 2 as the temperature of the chip increased by just 65 K. It was able to do this at low power (0.9 W/cm 2) of the pump. Since it was built on conventional silicon technology, the design was scalable to chips. Scientists believe that such efficiency may facilitate a generation of miniaturized energy efficient electronics.