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Huawei Wants to Surpass Moore’s Law Constraints With Its New Scaling System

Huawei Wants to Surpass Moore’s Law Constraints With Its New Scaling System

Huawei’s Tau Scaling Law introduces a time-based scaling framework to improve system performance and transistor density.

Written by Akash Dutta, Edited by Ketan Pratap | Updated: 25 May 2026 17:23 IST

Huawei Wants to Surpass Moore’s Law Constraints With Its New Scaling System

Photo Credit: Huawei

Huawei plans to combine hardware and software to achieve higher performance in chips

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Highlights

It proposes the usage of LogicFolding tech to surpass Moore’s Law
Instead of physical space, Tau makes use of time-based scaling
Huawei claims it can design 1.4nm process chipsets by 2031

The semiconductor industry is quickly reaching an inflection point. Last year, Samsung began mass production of the initial 2nm node for the Exynos 2600 chipsets. Other players, including TSMC, Qualcomm, MediaTek, and Intel, have also reached significant milestones when it comes to the technology. So far, Moore's Law is intact (at least in spirit). But beyond this, adhering to the law will become nearly impossible due to physical restraints and technology bottlenecks. As an alternative, Huawei has presented a new system dubbed the Tau Scaling Law.

The Problem With Moore's Law

Coined by Intel Co-Founder Gordon Moore in 1965, Moore's Law is an empirical observation that the number of transistors on a microchip doubles roughly every two years while the cost of a computer halves. Ever since, it has governed the exponential growth of computational power and the affordability of these devices. But six years later, most experts and technologists have acknowledged that Moore's Law is dead.

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It has been dead for some time now. The reality is that even with the 2nm process technology, Moore's Law is being kept alive in spirit (some might call it cheating). While the transistor density has doubled, the number of actual physical transistors on the wafer has only increased by 15 to 20 percent. The reason behind this is that the transistors do not really measure two nanometres.

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A silicon atom is about 0.2nm wide, which means 2nm is only 10 atoms across. At this size, quantum physics causes electrons to lean uncontrollably. So, the current 2nm process technology is only a marketing nomenclature to signify that the chips perform as if their sizes were scaled down to that size. In reality, companies are using new packaging architectures and stacking strategies, such as System-on-Integrated-Chips, to increase performance.

Enter Huawei's Tau Scaling Law

He Tingbo, President of the Semiconductor Business Department at Huawei, delivered a keynote speech at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) on Monday. During the speech, she presented the tau Scaling Law, a new guiding principle for the future development of the semiconductor industry.

In a newsroom post, Huawei said the law proposes “replacing geometric scaling with time scaling as a new guiding principle for the evolution of both semiconductors and electronic systems.” It also claimed that “innovative technologies such as LogicFolding can be used to continuously compress signal propagation delay and steadily improve transistor density.”

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The Tau Scaling Law proposes using time as a scaling mechanism by reusing physical hardware elements over processing or execution time within the same piece of silicon. Put simply, instead of asking, “How many physical transistors can be fit on this chip?”, it asks, “How can we reuse the existing transistors multiple times within a single execution cycle?”

So, while in Moore's Law, the only way to get 1,000 logic steps is by building 1,000 physical logic gates on the chip, with Tau's law, it can be reached by building a smaller set of highly flexible gates and dynamically “folding” them to process those steps sequentially in time.

And to answer the “how,” Huawei said innovative core technologies, such as LogicFolding and other architectures that use a multi-level software-hardware combination across devices, circuits, chips, and systems, can help. So, instead of breaking down the physical boundaries of traditional circuit layout, Huawei suggests using a software system to dynamically alter how many gates can be executed in a nanosecond.

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Interestingly, this is not just an exercise in theoretical physics either. During the keynote, the executive revealed that by 2031, Huawei will design chipsets based on the Tau Scaling Law that feature a transistor density that is equivalent to a 1.4nm process chip.

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Further reading: Huawei, Moores Law, Tau Scaling Law, Chipsets

Akash Dutta Email Akash Dutta

Akash Dutta is a Chief Sub Editor at Gadgets 360. He is particularly interested in the social impact of technological developments and loves reading about emerging fields such as AI, metaverse, and fediverse. In his free time, he can be seen supporting his favourite football club - Chelsea, watching movies and anime, and sharing passionate opinions on food. More